1. Field of the Invention
This invention relates to semiconductor chips, and more particularly, to maintaining accurate interrupt timestamps.
2. Description of the Relevant Art
A computing system such as a semiconductor chip may include multiple functional blocks or units, each capable of processing data. In some embodiments, the multiple functional units are individual dies on an integrated circuit (IC), such as a system-on-a-chip (SOC). In other embodiments, the multiple functional units are individual dies within a package, such as a multi-chip module (MCM). In yet other embodiments, the multiple functional units are individual dies or chips on a printed circuit board.
The computing system may also include multiple sources of interrupts. The multiple sources may include external peripheral devices and the internal functional units. An interrupt controller (IC) may receive an asserted interrupt and determine a corresponding priority level. In addition, the IC may identify a given one of the functional units in the computing system for handling the interrupt. For example, a graphics processor may be identified for processing video data associated with a given interrupt. Alternatively, a general-purpose processor or another single-instruction-multiple-data (SIMD) processor may be identified for processing audio data associated with a given interrupt.
At a later time, the IC may send an interrupt request to the identified processor. The processor may be in a low-power mode, such as an idle power-performance state (p-state). An appreciable amount of time may elapse for the processor to transition to an active p-state. Additionally, the priority level of the received interrupt may be below a threshold for the processor to immediately service it. The interrupt may be stored in a queue and wait for servicing. Again, an appreciable amount of time may elapse before the processor actually begins servicing the received interrupt.
When the interrupt is being serviced, either an interrupt service routine (ISR) or a device driver may direct the processor to send a request to the operating system (OS) for a current global value of elapsed time stored in a main time base counter. However, the OS may be busy with other operations. Additionally, the request for the current global elapsed time may have a priority level below a threshold for the OS to immediately service it. An appreciable amount of time may elapse before the ISR or the device driver receives the global elapsed time.
The interrupt to service may correspond to processing data that is to be synchronized with the processing of other data by another processor. For example, the processor may be directed by an audio device driver to process audio data that is to be synchronized with the processing of graphics data being processed by another processor. A media player may have sent the asserted interrupt to the IC. However, the multiple delays incorporated into the system between a first point-in-time the IC received the asserted interrupt from the source and a second point-in-time the ISR or the device driver received the global time base may be too great to synchronize the processing of two sets of data by two processors.
In view of the above, methods and mechanisms for maintaining accurate interrupt timestamps are desired.